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cat93c56, cat93c57 ? catalyst semiconductor, inc. 1 doc. no. md-1088 rev. q characteristics subject to change without notice 2-kb microwire serial cmos eeprom features ? high speed operation: 2mhz ? 1.8v to 5.5v supply voltage range ? selectable x8 or x16 memory organization ? sequential read ? software write protection ? power-up inadvertant write protection ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial and extended temperature ranges ? rohs-compliant 8-pin pdip, soic, tssop and 8-pad tdfn packages pin configuration pdip (l) soic (v, x) tssop (y) tdfn (vp2, zd4*) cs 1 8 v cc sk 2 7 nc di 3 6 org do 4 5 gnd soic (w*) nc 1 8 org v cc 2 7 gnd cs 3 6 do sk 4 5di * tdfn 3x3mm (zd4) and soic (w) rotated pin-out packages are available for cat93c57 and cat93c56, rev. e only (not recommended for new designs of cat93c56) pin function pin name function cs chip select sk clock input di serial data input do serial data output v cc power supply gnd ground org memory organization nc no connection description the cat93c56/57 is a 2-kb cmos serial eeprom device which is organized as either 128 registers of 16 bits (org pin at v cc ) or 256 registers of 8 bits (org pin at gnd). each register can be written (or read) serially by using the di (or do) pin. the cat93c56/57 features sequential read and self-timed internal write with auto- clear. on-chip power-on reset circuitry protects the internal logic against powering up in the wrong state. for ordering information details, see page 16. functional symbol cs sk di org do cat93c56 cat93c57 v cc gnd note: when the org pin is connect ed to vcc, the x16 organization is selected. when it is connected to ground, the x8 pin is selected. if the org pin is left unconnected, then am internal pullup device will select the x16 organization
cat93c56, cat93c57 doc. no. md-1088 rev. q 2 ? catalyst semiconductor, inc. characteristics subject to change without notice absolute maximum ratings (1) parameters ratings units storage temperature -65 to +150 c voltage on any pin with respect to ground (2) -0.5 to +6.5 v reliability characteristics (3) symbol parameter min units nend (4) endurance 1,000,000 program/ erase cycles tdr data retention 100 years d.c. operating characteristics, cat 93c56, die rev. g ? new product v cc = +1.8v to +5.5v, t a =-40c to +125c unless otherwise specified. symbol parameter test conditions min max units i cc1 power supply current (write) f sk = 1mhz, v cc = 5.0v 1 ma i cc2 power supply current (read) f sk = 1mhz, v cc = 5.0v 500 a t a = -40c to +85c 2 i sb1 power supply current (standby) (x8 mode) v in = gnd or v cc , cs = gnd org = gnd t a = -40c to +125c 4 a t a = -40c to +85c 1 i sb2 power supply current (standby) (x16 mode) v in = gnd or v cc , cs = gnd org = float or v cc t a = -40c to +125c 2 a t a = -40c to +85c 1 i li input leakage current v in = gnd to v cc t a = -40c to +125c 2 a t a = -40c to +85c 1 i lo output leakage current v out = gnd to v cc , cs = gnd t a = -40c to +125c 2 a v il1 input low voltage 4.5v v cc < 5.5v -0.1 0.8 v v ih1 input high voltage 4.5v v cc < 5.5v 2 v cc + 1 v v il2 input low voltage 1.8v v cc < 4.5v 0 v cc x 0.2 v v ih2 input high voltage 1.8v v cc < 4.5v v cc x 0.7 v cc + 1 v v ol1 output low voltage 4.5v v cc < 5.5v, i ol = 2.1ma 0.4 v v oh1 output high voltage 4.5v v cc < 5.5v, i oh = -400a 2.4 v v ol2 output low voltage 1.8v v cc < 4.5v, i ol = 1ma 0.2 v v oh2 output high voltage 1.8v v cc < 4.5v, i oh = -100a v cc - 0.2 v notes: (1) stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. these are stress ra tings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this specification is not implied. exposure to any absolute maximum rating for extended pe riods may affect device performance and re liability. (2) the dc input voltage on any pin should not be lower than -0.5v or higher than v cc + 0.5v. during transitions, the voltage on any pin may undershoot to no less than -1.5v or overshoot to no more than v cc + 1.5v, for periods of less than 20 ns. (3) these parameters are tested initially and after a design or process change that affects the parameter according to appropr iate aec-q100 and jedec test methods. (4) block mode, v cc = 5v, 25c
cat93c56, cat93c57 ? catalyst semiconductor, inc. 3 doc. no. md-1088 rev. q characteristics subject to change without notice d.c. operating characteristics, cat93c5 6/57, die rev. e ? mature product (cat93c56, rev. e ? not recommended for new designs) v cc = +1.8v to +5.5v, t a =-40c to +125c unless otherwise specified. symbol parameter test conditions min max units i cc1 power supply current (write) f sk = 1mhz, v cc = 5.0v 3 ma i cc2 power supply current (read) f sk = 1mhz, v cc = 5.0v 500 a i sb1 power supply current (standby) (x8 mode) v in = gnd or v cc , cs = gnd org = gnd 10 a i sb2 power supply current (standby) (x16 mode) v in = gnd or v cc , cs = gnd org = float or v cc 10 a i li input leakage current v in = gnd to v cc 1 a i lo output leakage current v out = gnd to v cc , cs = gnd 1 a v il1 input low voltage 4.5v v cc < 5.5v -0.1 0.8 v v ih1 input high voltage 4.5v v cc < 5.5v 2 v cc + 1 v v il2 input low voltage 1.8v v cc < 4.5v 0 v cc x 0.2 v v ih2 input high voltage 1.8v v cc < 4.5v v cc x 0.7 v cc + 1 v v ol1 output low voltage 4.5v v cc < 5.5v, i ol = 2.1ma 0.4 v v oh1 output high voltage 4.5v v cc < 5.5v, i oh = -400a 2.4 v v ol2 output low voltage 1.8v v cc < 4.5v, i ol = 1ma 0.2 v v oh2 output high voltage 1.8v v cc < 4.5v, i oh = -100a v cc - 0.2 v pin capacitance t a = 25c, f = 1mhz, v cc = 5v symbol test conditions min typ max units c out (1) output capacitance (do) v out = 0v 5 pf c in (1) input capacitance (cs, sk, di, org) v in = 0v 5 pf notes: (1) these parameters are tested initially and after a design or process change that affects the parameter according to appropr iate aec-q100 and jedec test methods.
cat93c56, cat93c57 doc. no. md-1088 rev. q 4 ? catalyst semiconductor, inc. characteristics subject to change without notice a.c. characteristics (1) , cat93c56, die rev. g ? new product v cc = +1.8v to +5.5v, t a = -40c to +125c, unless otherwise specified. limits symbol parameter min max units t css cs setup time 50 ns t csh cs hold time 0 ns t dis di setup time 100 ns t dih di hold time 100 ns t pd1 output delay to 1 0.25 s t pd0 output delay to 0 0.25 s t hz (2) output delay to high-z 100 ns t ew program/erase pulse width 5 ms t csmin minimum cs low time 0.25 s t skhi minimum sk high time 0.25 s t sklow minimum sk low time 0.25 s t sv output delay to status valid 0.25 s sk max maximum clock frequency dc 2000 khz a.c. characteristics (1) , cat93c56/57, die rev. e ? mature product (cat93c56 rev. e - not recommended for new designs) limits v cc = 1.8v - 5.5v v cc = 2.5v - 5.5v v cc = 4.5v - 5.5v symbol parameter min max min max min max units t css cs setup time 200 100 50 ns t csh cs hold time 0 0 0 ns t dis di setup time 400 200 100 ns t dih di hold time 400 200 100 ns t pd1 output delay to 1 1 0.5 0.25 s t pd0 output delay to 0 1 0.5 0.25 s t hz (2) output delay to high-z 400 200 100 ns t ew program/erase pulse width 10 10 10 ms t csmin minimum cs low time 1 0.5 0.25 s t skhi minimum sk high time 1 0.5 0.25 s t sklow minimum sk low time 1 0.5 0.25 s t sv output delay to status valid 1 0.5 0.25 s sk max maximum clock frequency dc 250 dc 500 dc 1000 khz notes : (1) test conditions according to ?a.c. test conditions? table. (2) these parameters are tested initially and after a design or process change that affects the parameter according to appropri ate aec-q100 and jedec test methods.
cat93c56, cat93c57 ? catalyst semiconductor, inc. 5 doc. no. md-1088 rev. q characteristics subject to change without notice power-up timing (1) (2) symbol parameter max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms notes : (1) these parameters are tested initially and after a design or pr ocess change that affects the parameter according to appropri ate aec-q100 and jedec test methods. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. a.c. test conditions input rise and fall times 50 ns input pulse voltages 0.4v to 2.4v 4.5v ? v cc ? 5.5v timing reference voltages 0.8v, 2.0v 4.5v ? v cc ? 5.5v input pulse voltages 0.2v cc to 0.7v cc 1.8v ? v cc ? 4.5v timing reference voltages 0.5v cc 1.8v ? v cc ? 4.5v output load current source i olmax /i ohmax ; cl=100pf device operation the cat93c56/57 is a 2048-bit nonvolatile memory intended for use with industry standard micropro- cessors. the cat93c56/57 can be organized as either registers of 16 bits or 8 bits. when organized as x16, seven 10-bit instructi ons for 93c57 or seven 11- bit instructions for 93c56 control the reading, writing and erase operations of the device. when organized as x8, seven 11-bit instructions for 93c57 or seven 12-bit instructions for 93c56 control the reading, writing and erase operations of the device. the cat93c56/57 operates on a single power supply and will generate on chip, the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the risi ng edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. the serial communication protocol follows the timing shown in figure 1. the ready/busy status can be determined after the start of internal write cycle by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the ne xt instruction. if necessary, the do pin may be placed back into a high impedance state during chip select by shifting a dummy ?1? into the di pin. the do pin will enter the high impedance state on the rising edge of the clock (sk). placing the do pin into the high impedance state is recommended in applications where the di pin and the do pin are to be tied together to form a common di/o pin. figure 1. sychronous data timing sk di cs d o t dis t pd0, t pd1 t csmin t css t dis t dih t skhi t csh valid valid data valid t sklow
cat93c56, cat93c57 doc. no. md-1088 rev. q 6 ? catalyst semiconductor, inc. characteristics subject to change without notice the format for all instructions sent to the device is a logical ?1? start bit, a 2-bit (or 4-bit) opcode, 7-bit address (cat93c57) / 8-bit address (cat93c56) (an additional bit when organized x8) and for write operations a 16-bit data field (8-bit for x8 organi? zations). the instruction format is shown in instruction set table. instruction set address data instruction device type start bit opcode x8 x16 x8 x16 comments read 93c56 (1) 1 10 a8-a0 a7-a0 93c57 1 10 a7-a0 a6-a0 read address an?a0 erase 93c56 (1) 1 11 a8-a0 a7-a0 93c57 1 11 a7-a0 a6-a0 clear address an?a0 write 93c56 (1) 1 01 a8-a0 a7-a0 d7-d0 d15-d0 93c57 1 01 a7-a0 a6-a0 d7-d0 d15-d0 write address an?a0 ewen 93c56 (1) 1 00 11xxxxxxx 11xxxxxx 93c57 1 00 11xxxxxx 11xxxxx write enable ewds 93c56 (1) 1 00 00xxxxxxx 00xxxxxx 93c57 1 00 00xxxxxx 00xxxxx write disable eral 93c56 (1) 1 00 10xxxxxxx 10xxxxxx 93c57 1 00 10xxxxxx 10xxxxx clear all addresses wral 93c56 (1) 1 00 01xxxxxxx 01xxxxxx d7-d0 d15-d0 93c57 1 00 01xxxxxx 01xxxxx d7-d0 d15-d0 write all addresses note: (1) address bit a8 for 256x8 organization and a7 for 128x16 organiza tion are "don't care" bits, but must be kept at either a "1 " or "0" for read, write and erase commands.
cat93c56, cat93c57 ? catalyst semiconductor, inc. 7 doc. no. md-1088 rev. q characteristics subject to change without notice read upon receiving a read command and an address (clocked into the di pin), the do pin of the cat93c56/57 will come out of the high impedance state and, after se nding an initial dummy zero bit, will begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ). for the cat93c56/57, after the initial data word has been shifted out and cs remains asserted with the sk clock continuing to togg le, the device will auto- matically increment to the next address and shift out the next data word in a sequential read mode. as long as cs is continuously asserted and sk continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. in the sequential read mode, only the initial data word is preceeded by a dummy zero bit. all subsequent data words will follow without a dummy zero bit. the read instruction timing is illu strated in figure 2. erase/write enable and disable the cat93c56/57 powers up in the write disable state. any writing after power-up or after an ewds (erase/write disable) instruction must first be preceded by the ewen (erase/write enab le) instruction. once the write instruction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all cat93c56/57 write and erase instructions, and will prevent any accidental writing or clearing of the device. data can be read normally from the device regardless of the write enable/disable status. the ewen and ewds instructions timing is shown in figure 3. figure 2. read instruction timing figure 3. ewen/ewds instruction timing sk cs di do high-z 11 0 a n a n?1 a 0 dummy 0 d 15 . . . d 0 or d 7 . . . d 0 address + 1 d 15 . . . d 0 or d 7 . . . d 0 address + 2 d 15 . . . d 0 or d 7 . . . d 0 address + n d 15 . . . or d 7 . . . don't care t pd0 cs di standby 10 0 * * enable = 11 disable = 00 sk
cat93c56, cat93c57 doc. no. md-1088 rev. q 8 ? catalyst semiconductor, inc. characteristics subject to change without notice write after receiving a write command (figure 4), address and the data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clo cking clear and data store cycle of the memory location specified in the instruction. the clocking of the sk pin is not necessary after the device has entered the self clo cking mode. the ready/busy status of the cat93c56/57 can be determined by selecting the device and polling the do pin. since this device features auto-clear before write, it is not necessary to erase a memory location before it is written into. erase upon receiving an erase command and address, the cs (chip select) pin must be deasserted for a minimum of t csmin (figure 5). the falling edge of cs will start the self clocking clear cycle of the selected memory location. the clocking of the sak pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c56/57 can be determined by selecting the device and polling the do pin. once cleared, the c ontent of a cleared location returns to a logical ?1? state. figure 4. write instruction timing figure 5. erase instruction timing sk cs di do t csmin standby high-z high-z 101 a n a n-1 a 0 d n d 0 busy ready status verify t sv t hz t ew sk cs di do standby high-z high-z 1 a n a n-1 busy ready status verify t sv t hz t ew t cs 11 a 0
cat93c56, cat93c57 ? catalyst semiconductor, inc. 9 doc. no. md-1088 rev. q characteristics subject to change without notice erase all upon receiving an eral command (figure 6), the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs w ill start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c56/57 can be deter- mined by selecting the device and polling the do pin. once cleared, the contents of all memory bits return to a logical ?1? state. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of t csmin (figure 7). the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c56/57 can be determined by selecting th e device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. figure 6. eral instruction timing figure 7. wral instruction timing sk cs di do standby t cs high-z high-z 10 1 busy ready status verify t sv t hz t ew 00 status verify sk cs di do standby high-z 10 1 busy ready t sv t hz t ew t csmin d n d 0 0 0
cat93c56, cat93c57 doc. no. md-1088 rev. q 10 ? catalyst semiconductor, inc. characteristics subject to change without notice package outline drawings pdip 8-lead 300mils (l) (1) notes: (1) all dimensions are in millimeters. (2) complies with jedec standard ms-001. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. e1 d a l eb b2 a1 a2 e eb c top view side view end view pin # 1 identification symbol min nom max a5.33 a1 0.38 a2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 d 9.02 9.27 10.16 e 7.62 7.87 8.25 e 2.54 bsc e1 6.10 6.35 7.11 eb 7.87 10.92 l 2.92 3.30 3.80
cat93c56, cat93c57 ? catalyst semiconductor, inc. 11 doc. no. md-1088 rev. q characteristics subject to change without notice soic 8-lead 150mils (v, w) (1) notes: 1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec standard ms-012. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. e1 e a a1 h l c e b d pin # 1 identification top view side view end view a 1.35 1.75 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 5.80 6.20 e1 3.80 4.00 e 1.27 bsc h 0.25 0.50 l 0.40 1.27 0o 8o symbol min nom max
cat93c56, cat93c57 doc. no. md-1088 rev. q 12 ? catalyst semiconductor, inc. characteristics subject to change without notice soic 8-lead eiaj (208mils) (x) (1) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with eiaj edr-7320 for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. e1 eb side view top view e d pin#1 identification end view a1 a l c symbol min nom max a2.03 a1 0.05 0.25 b0.36 0.48 c0.19 0.25 d5.13 5.33 e7.75 8.26 e1 5.13 5.38 e 1.27 bsc l0.51 0.76 0o 8o
cat93c56, cat93c57 ? catalyst semiconductor, inc. 13 doc. no. md-1088 rev. q characteristics subject to change without notice tssop 8-lead 4.4mm (y) (1) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. for current tape and reel information, download the pdf file from: http: / /www.catsemi.com/documents/tapeandreel.pdf. a2 e1 e a1 e b d c a top view side view end view 1 l1 l symbol min nom max a1.20 a1 0.05 0.15 a2 0.80 0.90 1.05 b0.19 0.30 c0.09 0.20 d 2.90 3.00 3.10 e 6.30 6.40 6.50 e1 4.30 4.40 4.50 e 0.65 bsc l1.00 ref l1 0.50 0.60 0.75 10 8
cat93c56, cat93c57 doc. no. md-1088 rev. q 14 ? catalyst semiconductor, inc. characteristics subject to change without notice tdfn 8-pad 2 x 3mm (vp2) (1) notes: (1) all dimensions are in millimeters. (2) complies with jedec standard mo-229. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. pin#1 identification e2 e a3 eb d a2 top view side view bottom view pin#1 index area front view a1 a l d2 symbol min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a2 0.45 0.55 0.65 a3 0.20 ref b 0.20 0.25 0.30 d 1.90 2.00 2.10 d2 1.30 1.40 1.50 e 2.90 3.00 3.10 e2 1.20 1.30 1.40 e 050 typ l 0.20 0.30 0.40
cat93c56, cat93c57 ? catalyst semiconductor, inc. 15 doc. no. md-1088 rev. q characteristics subject to change without notice tdfn 8-pad 3 x 3mm (zd4) (1) notes: (1) all dimensions are in millimeters. (2) complies with jedec mo-229. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. e2 a3 eb a a1 side view bottom view e d top view pin#1 index area pin#1 id front view a1 a l d2 symbol min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 ref b 0.23 0.30 0.37 d 2.90 3.00 3.10 d2 2.20 ? 2.50 e 2.90 3.00 3.10 e2 1.40 ? 1.80 e0.65typ l 0.20 0.30 0.40
cat93c56, cat93c57 doc. no. md-1088 rev. q 16 ? catalyst semiconductor, inc. characteristics subject to change without notice example of ordering information cat93c56, die rev. g, new product notes: (1) all packages are rohs-compli ant (lead-free, halogen-free). (2) the standard lead finish is nipdau. (3) the device used in the above example is a cat93c56vi-gt3 (soic, industrial temperature, nipdau, tape & reel). (4) for soic, eiaj (x) package the standard lead finish is matte-t in. this package is available in 2,000 pcs/reel, i.e. cat93c5 6xi-t2. (5) for additional package and temperature options, please contact your nearest ca talyst semiconductor sales office. cat93c56/57, die rev. e, mature product (cat93c56, rev. e ? not recommended for new designs) notes: (1) all packages are rohs-comp liant (lead-free, halogen-free). (2) the standard finish is nipdau. (3) the device used in the above example is a cat93c56vi-1.8-gt3 (soic green package, industrial temperature, 1.8 volt to 5.5 v olt operating voltage, nipdau finish, tape & reel.) (4) product die revision letter is marked on top of the package as a suffix to t he production date code (e.g., aywwe). for addi tional informa- tion, please contact your catalyst sales office. (5) for soic, eiaj (x) package the standard lead finish is matte-t in. this package is available in 2,000 pcs/reel, i.e. cat93c5 6xi-t2. (6) for additional package and temperature options, please contact your nearest ca talyst semiconductor sales office. prefix device # suffix cat 93c56 v i -1.8 -g t3 rev e ( 4) operating voltage blank : v cc = 2.5v to 5.5v 1.8: v cc = 1.8v to 5.5v company id product numbe r 93c56 93c57 temperature range i = industrial (-40oc to 85oc) a = automotive (-40oc to 105oc) e = extended ( -40oc to 125oc ) lead finish blank: matte-tin g: nipdau die revision 93c56: e 93c57: e package l: pdip v: soic, jedec w: soic, jedec x: soic, eiaj (5) y: tssop zd4: tdfn (3x3mm) tape & reel t: tape & reel 2: 2,000 units/reel (5) 3: 3 , 000 units/reel prefix device # suffix cat 93c56 v i -g t3 company id product numbe r 93c56 temperature range i = industrial (-40oc to +85oc) e = extended (-40oc to +125oc) lead finish blank: matte-tin g: nipdau package l: pdip v: soic, jedec x: soic, eiaj (4) y: tssop vp2: tdfn (2x3mm) tape & reel t: tape & reel 2: 2,000 units/reel (4) 3: 3 , 000 units/reel
cat93c56, cat93c57 ? catalyst semiconductor, inc. 17 doc. no. md-1088 rev. q characteristics subject to change without notice revision history date rev. comments 05/14/04 l new data sheet created from cat9 3c46/56/57/66/86. parts cat93c56, cat93c56, cat93c57, cat93c56/57, cat93c76 and cat93c86 have been separated into single data sheets 10/13/06 m updated instruction set 03/18/05 n updated description 10/13/06 o update features update pin configuration update functional symbol update pin functions update d.c. operating characteristics (v cc range) update a.c. characteristics (v cc range) update ordering information 08/21/07 p updated features/description remove "die rev e" from the title update pin configuration / packages update absolute maximum rating update reliability characteristics update d.c. operating characteristics added d.c. / a.c. characteri stics for cat93c56 die rev g rearrange / format text and figures update package outline drawings added example of ordering information for cat93c56 die rev. g add md- to document number 04/10/08 q add extended temperature range update package outline drawings
copyrights, trademarks and patents ? catalyst semiconductor, inc. trademarks and register ed trademarks of catalyst semiconductor include each of the following: adaptive analog?, beyond memory?, dpp?, ezdim?, ldd?, minipot?, quad-mode? and quant um charge programmable? i 2 c? is a trademark of philips corporati on. catalyst semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. catalyst semiconductor has been issued u. s. and foreign patents and has patent applicat ions pending that protect its products. catalyst semiconductor makes no warranty, representation or guar antee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its pro ducts will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semiconduct or product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any produ ct or service descr ibed herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in pr oduction or offered for sale. catalyst semiconductor advises customers to obtain the current version of the rele vant product informati on before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 document no: md-1088 fax: 408.542.1200 revision: q www.catsemi.com issue date: 04/10/08

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